Non-volatile memory is memory that can continue to store data after power is no longer provided to the memory. “Flash memory,” called this because data can be erased from multiple memory cells simultaneously, is an example of non-volatile memory. A typical flash memory comprises an array of memory cells having the cells arranged in rows and columns of memory. The array is broken down into blocks of memory cells. Although each of the cells within a block can be electrically programmed to store data individually, data is erased from the cells at the block level.
A common example of flash memory is NAND flash memory. The array of memory cells for NAND flash memory devices are arranged such that a control gate of each memory cell of a row of the array is connected to a word line. However, each memory cell is not directly connected to a column bit line. Instead, the memory cells of the array are arranged together in strings (“NAND strings”), with the memory cells connected together in series, source to drain, between a source line and a column bit line. The NAND strings can have as many as 32 memory cells between the source line and the column bit line.
The memory array for NAND flash memory devices is then accessed by a row decoder activating a row of memory cells by selecting the word line connecting the control gates of the memory cells. In addition, the word lines connected to the control gates of unselected memory cells of each string are driven so that the respective memory cell passes current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each series connected string, restricted only by the selected memory cells of each string. This places the current-encoded data values of the row of selected memory cells on the column bit lines to be sense and amplified before being output as data, as well known.
NAND flash memory is designed to serve as a low cost solid state mass storage medium. As a result, standard specifications for NAND flash memory allow a manufacturer to sell NAND flash devices having a percentage of non-functional blocks of memory, or “initial bad blocks” of memory. Allowing for bad blocks of memory increases the effective yield of marketable devices, thereby lowering costs. The bad blocks do not affect the performance of good blocks of memory because each block is independently accessible.
Generally the process of identifying initial bad blocks occurs during testing by the manufacturer. A conventional manner of marking the bad blocks is to program non-FF data at specific locations within each bad block. Upon use by a user, a bad block disable process is performed. The specific locations are queried to identify which blocks of memory are bad. Control logic included in the memory device identifies the bad blocks by checking for the non-FF data, and if present, the block can be disabled using a conventional technique of setting a latch in the respective block decoder circuits for the bad block. Setting the latch prevents access to the bad block and provides a hardware mechanism for disabling bad blocks prior to operation.
Although the technique of using non-FF data is effective in marking initial bad blocks, some users choose not to read the array for the bad block information prior to use, and simply erase the entire array. As a result, the non-FF data programmed to identify the bad blocks are erased, thus, eliminating any way to identify which blocks are bad after the erasing process.
In order to enable identification of bad blocks even in the case where the entire memory array is erased prior to use, a technique of programming initial bad block information in a user-inaccessible memory has been used. One technique for programming bad block information to user-inaccessible memory is to program the initial bad block information into specific circuits designed to store this information. An example of this type of circuit is described in U.S. Pat. No. 5,864,499 to Roohparvar et al. The circuits are small arrays of non-volatile memory cells having dedicated sense amplifiers. The memory cells can be programmed and function as “fuses” to store information identifying the initial bad blocks. One problem resulting from this approach is that as the number of memory blocks in a memory device increases, and there are a greater absolute number of bad blocks, the number of the dedicated “fuse circuits” must also increase. The additional fuse circuits occupy more space on the die, which is generally undesirable.
Another approach to storing initial bad block information is to store the information at locations in the memory array that are inaccessible to the user. For example, a One-Time Programmable (“OTP”) area can be programmed with the initial bad block information. The OTP area is restricted from access by the user. The OTP area is typically functionally the same as any other memory block in the array, that is, it is not specially designed for the purpose of storing bad block information. Information cataloging the bad blocks identified during testing can be stored in the OTP area for use by the controller during initialization to set latches in the respective block decoders and disable access to the bad blocks.
In the technique where bad block information is programmed in a user-inaccessible memory block, a voltage detection circuit is typically used to trigger the bad block disable process. That is, when the voltage detection circuit detects an increasing device supply voltage VCC that exceeds a trigger voltage, the control logic begins the bad block disable process. The trigger voltage is selected low enough so that the bad blocks of memory are disabled and the device is ready for use by the time VCC reaches a specified range of operation. Taking into account process variations which can affect the trigger voltage at which the voltage detection circuit triggers the control logic to begin the bad block disable process, a typical trigger voltage is 2.5 Volts for a nominal VCC of 3.3 Volts (acceptable voltage range of 2.7-3.6 Volts).
A problem with this approach results from the desire to operate memory devices at lower device supply voltages, for example, at a nominal VCC of 1.8 Volts (acceptable voltage range of 1.5-2.0 Volts). A suitable trigger voltage that takes into account process variations and the relationship with VCC so that the device is operational when device supply voltage stabilizes would need to be as low 1.2 Volts. At this voltage level, however, reading data stored in the memory array, of which the OTP area is a part, is unreliable. Consequently, reading bad block information stored in the OTP area at this lower voltage may result in incorrect data, resulting in erroneous identification of bad blocks.
Additionally, voltage detection circuits that can accurately and consistently detect lower trigger voltages are difficult to design for applications where the reference voltage is derived from the same voltage being monitored, namely, VCC.
Although dedicated “fuse circuits” could be reliably read at lower trigger voltages, storing bad block information in the dedicated circuits is undesirable because the circuits occupy more space on the die than is desirable, as previously discussed.
Another approach is to provide a reset pin on the memory device that can be used to trigger the read-latch set operation. However, providing a reset signal to the reset pin of the device would need to be supported by a system memory controller, thus, complicating the architecture of the system, not to mention that it is generally undesirable to add pins to a device due to package constraints.
Therefore, there is a need for an alternative system and method for initiating a bad block disable process that can reliably disable access to bad blocks of memory.